PURPOSE
The purpose of this exercise is to conduct a study of a Moore type state machine.
DESCRIPTION
You want to design a sequence detector that recognizes the input sequence "1 Æ 0 Æ 1 Æ 1 '.
• The entry is called 'a'.
• And the 'S' output.
OPEN PROJECT NAVIGATOR
On your desktop find the icon 'Project Navigator', double click and open the environment with the latest project with which we worked.
CREATING NEW PROJECT
From 'File-> New Project'set the first parameters of the project as the name 'DETECTOR' and type 'HDL'. We click on 'Next '.
Configure Family, Device, Housing, Speed, synthesizer, simulator and simulation language.
LIST NEW SOURCE
We will add a source to our project, with the name 'DETECTOR', using a formal language display state machine chart.
LIST PORTS OF ENTRY AND EXIT OF THE MACHINE
To do this we enter 'Options-> Variable'. Be added by putting the name in the 'Name ', setting the type, the active and whether it will be a pin or an internal node. Later we click the 'Add / Modify'.
LIST STATES, TRANSITIONS AND RESET
VERIFICATION
Verify the correct operation of automatically creating a 'test bench'.
We click on the button 'State Bench' and generate the file 'test bench' passing through the states:
To begin and we will create the file extension (*. vhdl).
VHDL code shows in a window where we can see how the entity is formed by the inputs 'a', 'CLK', 'RESET' and the 'S' output.
Save the PLC and left the program and add the file to the project.
SUMMARY OF THE DETECTOR
SUMMARY
Double click on the process "Synthesize" XST 'situated in the process window and we performed the synthesis of the PLC.
PLACEMENT (Translate)
Make all necessary steps to convert the input netlist file in a proprietary format NGD using an internal representation of the technology being used.
To run the utility we get up 'Translate' and double click.
CONNECTIONS (Fit)
Fit maps the logic defined by the NGD file into the CPLD resources, such as logic cells, I / OB 's and other components. The process output is a file that is physically VM6 connection of the components in the CPLD.
To run the utility we get up 'Fit' and double click.
We found that everything was properly inspecting the report 'fitter report. "
Finally program the device.
https://sites.google.com/site/franbc0100/DETECTOR.jed?attredirects=0&d=1
The purpose of this exercise is to conduct a study of a Moore type state machine.
DESCRIPTION
You want to design a sequence detector that recognizes the input sequence "1 Æ 0 Æ 1 Æ 1 '.
• The entry is called 'a'.
• And the 'S' output.
OPEN PROJECT NAVIGATOR
On your desktop find the icon 'Project Navigator', double click and open the environment with the latest project with which we worked.
CREATING NEW PROJECT
From 'File-> New Project'set the first parameters of the project as the name 'DETECTOR' and type 'HDL'. We click on 'Next '.
Configure Family, Device, Housing, Speed, synthesizer, simulator and simulation language.
LIST NEW SOURCE
We will add a source to our project, with the name 'DETECTOR', using a formal language display state machine chart.
LIST PORTS OF ENTRY AND EXIT OF THE MACHINE
To do this we enter 'Options-> Variable'. Be added by putting the name in the 'Name ', setting the type, the active and whether it will be a pin or an internal node. Later we click the 'Add / Modify'.
LIST STATES, TRANSITIONS AND RESET
Verify the correct operation of automatically creating a 'test bench'.
We click on the button 'State Bench' and generate the file 'test bench' passing through the states:
VHDL code shows in a window where we can see how the entity is formed by the inputs 'a', 'CLK', 'RESET' and the 'S' output.
Save the PLC and left the program and add the file to the project.
SUMMARY OF THE DETECTOR
SUMMARY
Double click on the process "Synthesize" XST 'situated in the process window and we performed the synthesis of the PLC.
Make all necessary steps to convert the input netlist file in a proprietary format NGD using an internal representation of the technology being used.
To run the utility we get up 'Translate' and double click.
CONNECTIONS (Fit)
Fit maps the logic defined by the NGD file into the CPLD resources, such as logic cells, I / OB 's and other components. The process output is a file that is physically VM6 connection of the components in the CPLD.
To run the utility we get up 'Fit' and double click.
We found that everything was properly inspecting the report 'fitter report. "
Finally program the device.
https://sites.google.com/site/franbc0100/DETECTOR.jed?attredirects=0&d=1
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