TADXC9572

The electronics Dijital to left behind the design with discrete devices and fixed function is immersed in the world of rpogramables logic devices (PLD's).


To perform complex, using custom-designed circuits that serve only to an application, are called ASIC's (Aplicaction Specific Integrated Circuit), which occupies less space, more reliable, consume less energy and are very difficult to copy.


One method of ASIC's, are user-programmable circuits IFPC's (Field Programmable inegrated Circuits). They have copied our days ek market, offering low cost solutions, with a short development time less risk than dedicated circuits.

The term FIP includes CI's NIO detinados logical applications. FPIC's Son

"The reports

-Microcontrollers 
"The LDP` s 
"The CPLD's 
"The FPGA's

Generally, ols designers, when developing a logic circuit, have three alternatives:


-Using CI, s (integrated circuits) discrete logic (TTL, CMOS, etc.). 
-Using CI's adptados whole or in part to the needs of the user (ASIC's) 
"Using programmable logic devices or PLD's (Programmable Logic Devices) by the user (PROM's, GAL's, PAL's, CPLD's, FPGA's, etc).

Didactic application card 'Tad-XC9572, "based on the XC9500 CPLD family of XILINNX, and comprehensive documentation can, among other things:


-Start students porofesional formation in the world of programmable technology.

-To guide teachers in their teaching cycles.
-To help engineering students to develop their projects.
-Provide professional design their rpototipos.
-Minimize the learning problems because:


           * The chip is already mounted and accompanied by a periphery of components that facilitate their study.

           * The construction and operation of the CPLD is translated into Spanish.
           * The basic tools for various development projects, hardware environment and software, are fully explained through didactic examples.
Diagram to bloks

 INTRODUCTION




The difficulty with any documentode this type is the wide range of knowledge, direct and indirect, which are accurate to have to reach an objectiv, ie, its management or application.


Our task is to simplify, as far as possible all these porblem that can lead to a neglect or disinterest towards the goal that concerns us.


Without further dedicate these lines to show and present the most important work and help them have a simplified overview of the elements of the document.


The document is divided into six sections which deal exhaustive different accrued knowledge acquired for the management of CPLD's.



1-Introduction to Logic devices porgramas
2-technical specification of the XC9572 CPLD family from Xilinx XC9500
3-You ...
Technical Features 4-card application didactic 'TAD-XC9572'
5-design process
6-collectionof ejerccios poracticos

   INTRODUCTION TO PROGRAMMABLE LOGIC DEVICES:

Generally, designers, when developing a logic circuit, have two alternatives:

1.Make CIS (integrated circuits) of discretra logic (TTL, CMOs.etc).
CIS 2.Using wholly or partially adapted to the needs of the user (ASIC's).1 tipos de ASIC´s

For very complex achievements require a high number of fixed-function ICs are used as designed circuits. These are called application-specific IC or ASIC (Application Specific Integrated Circuit).


Generally, the ASIC's:

       -take up less space.
       -are more reliable.
       -in large series, are cheaper than the fixed function.
       -are very difficult to copy.


The ASIC's are divided into the following categories:

1.1 Full custom
* is designed at the request of a client to solve a particular application.
* everything is hand made at the transistor and layout
* carry a high development cost
* only justified for very high production volumes
* used for months or years for building

1.2 Semi custom

1.2.1-Gate Array (Matrix doors)

         The manufacturers adisposicion its customers a series of macros that can be used immediately and others that can build themselves.

* The MACROS b'asicas are clusters of cells that perform basic functions (NOT, AND, SR, JKetc.)
* Once you get past all previous stages, the client sends the general documentation that the manufacturer built a first prototype.
* You only have to make the final mask that defines the connections between gates
* design can take weeks or months and is expensive.

Standard 1.2.2.-cell (standard cell)

Similar to gate arrays, but with the advantage of not working to not work with single doors.

Collections are available from different parts of circuits that have been purified as

-logic gates
Static Ram
MSI-Circuits
Log-files, etc ...

* The user has to assemble these circuits, tested and finally, send the documentation to the manufacturer.
* You have to make masks for all processes of production of ICs.
* Periods and development costs are higher than gate arrays.



1.3.-FPIC 's

* Are chip's programmable by the user through comercioales programmers.
* They offer low cost solutions
* The development time is short and with less risk than GATE ARRAY and STANDARD CELL.


              1.3.1-PLD and SPLD

                    (Simple Programmable Logic Device) are small ASIC's configurable by the user able to perform a given logic function.



Compared with standard circuits SSI / MSI

* Reduce the cost of the circuit.
* reducing the number of chip'sy by tasnto the size of the plates.

This results in:

-increase the operating speed of the circuit.
-increased reliability (decrease of interconnection).
cost-reduction circuit (PCB area).
-reduction in consumption.

* Flexibility

-can change the functionality of the design to add new features without changing the PCB.
* is more difficult to copy (intellectual property). Incorporate a programmable security bit for protection design
* Simplifies the work of designer and accelerates the design process
-design tools are used by computer ASSISTED.

* The typical structure consists of 'sum of products'

-Matrix + Matrix programmable AND fixed OR
"You can implement a function of n inputs cualqier less than p product terms (p <2n)
* interconnections are scheduled. The CPLD's birth
-The number of interrupts = (2n x px m)
1.3.2-CPLD (Programmable Logic Device compiler)

In the late 80's of last century, the macrocells of the PDL's were complicating their functions and IC pin increased their numbers, being able to deploy up to 2 or 3 PLD

Void of cover integration of doors,
chip, which is between the programmable logic simple (250 doors) and doors FPGA's5000 minimum).
Basically, the internal architecture of a CPLD is made up of blocks of input and output control blocks connected to macrocells.

1.3.3-FPGA (field programmable gate array)

These devices combine the advantages of technology SEMICUSTON of GATE ARRAY's with the flexibility and ease of programmable logic design.


In fact, the philosophy of designing a FPGA is similar to that of a GATE ARRAY because, basically, is composed of independent cells that can be programmable interconnect with each other through channels also programmable, offers calm giving out complex functions.


  While in a GATE ARRAY working at the silicon level predifundido (semicustom) in a working-level FPGA programmable logic.

* Advantages and disadvantages
an FPGA on a GATE ARRAY.

drawbacks:

-Low speed, the less optimization, lower density
-Major delays
"Ignorance of the value of relatardos to chip rpogramacion


advantages:

-Easy and quick programming
-Cost of the unit (do not need mass production to be profitable)

Internal structure:
  Internally everything is basically PLD

-Tickets
-Out
DNA-array (fixed or variable)
OR-array (fixed or variable)
-macrocell (optional output)

fusibles1.1

In addition, we will study the PALCE22V10 (24 pins) because it enjoys more popularity in the world of programmable loqica.